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  www.siliconstandard.com 1 of 5 p-channel enhancement-mode power mosfet low gate-charge bv dss -20v simple drive requirement r ds(on) 65mw fast switching i d -4.2a description the SSM2305GN is in a sot-23-3 package, which is widely used for lower power commercial and industrial surface mount applications. this device is suitable for low-voltage applications such as dc/dc converters and and g d s absolute maximum ratings symbol units v ds v v gs v i d @ t a =25c i d @ t a =70c i dm p d @ t a =25c w/c t stg t j symbol value unit r qja maximum thermal resistance, junction-ambient 3 90 c/w parameter rating drain-source voltage -20 gate-source voltage continuous drain current 3 -4.2 a continuous drain current 3 -3.4 a pulsed drain current 1,2 -10 a operating junction temperature range -55 to 150 c linear derating factor 0.01 storage temperature range total power dissipation 1.38 w -55 to 150 c thermal data parameter 12 pb-free; rohs compliant. d g s sot-23-3 general switching applications. ssm230 5 gn 2/16/2005 re v.2.1
www.siliconstandard.com 2 of 5 SSM2305GN 2/16/2005 re v.2.1 electrical characteristics (at tj = 25c, unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -20 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =-1ma - -0.1 -v/c r ds(on) static drain-source on-resistance v gs =-10v, i d =-4.5a - - 53 mw v gs =-4.5v, i d =-4.2a - - 65 mw v gs =-2.5v, i d =-2.0a - - 100 mw v gs =-1.8v, i d =-1.0a - - 250 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -0.5 - - v g fs forward transconductance v ds =-5v, i d =-2.8a - 9 - s i dss drain-source leakage current (t j =25 o c) v ds =-20v, v gs =0v - - -1 ua drain-source leakage current (t j =55 o c) v ds =-16v, v gs =0v - - -10 ua i gss gate-source leakage v gs =- - na q g total gate charge 2 i d =-4.2a - 10.6 - nc q gs gate-source charge v ds =-16v - 2.32 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 3.68 - nc t d(on) turn-on delay time 2 v ds =-15v - 5.9 - ns t r rise time i d =-4.2a - 3.6 - ns t d(off) turn-off delay time r g =6w , v gs =-10v - 32.4 - ns t f fall time r d =3.6w - 2.6 - ns c iss input capacitance v gs =0v - 740 - pf c oss output capacitance v ds =-15v - 167 - pf c rss reverse transfer capacitance f=1.0mhz - 126 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-1.2a, v gs =0v - - -1.2 v trr reverse recovery time i s =-4.2a, v gs =0v, - 27.7 - ns qrr reverse recovery charge di/dt=100a/s - 22 - nc notes: 1.pulse width limited by maximum junction temperature. 2.pulse width < 300us, duty cycle < 2%. 3.surface-mounted on 1 in 2 copper pad on fr4 board; 270c/w when mounted on minimum copper pad. 12v 100
www.siliconstandard.com 3 of 5 ssm230 5 gn 2/16/2005 re v.2.1 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d = -4.2a v gs = -4.5v 0 10 20 30 40 024681 0 -v ds , drain-to-source voltage (v) -i d , drain current (a) -4.0v t a =25 o c -5.0v -3.0v v g = -2.0v 0 4 8 12 16 20 24 28 32 36 02468 -v ds , drain-to-source voltage (v) -i d , drain current (a) v g = -2.0v -4.0v -5.0v -3.0v t a =150 o c 0.01 0.1 1 10 100 0 0.4 0.8 1.2 1.6 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 0 0.5 1 1.5 -50 0 50 100 150 t j , junction temperature ( o c) -v gs(th) (v) 40 80 120 160 0123456 -v gs , gate-to-source voltage (v) r ds(on) ( w) i d =-4.2a t a =25 o c
www.siliconstandard.com 4 of 5 ssm230 5 gn 2/16/2005 re v.2.1 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time circuit fig 12. gate charge circuit 0 2 4 6 8 10 12 0 5 10 15 20 25 q g , total gate charge (nc) -v gs , gate to so ur ce voltage (v) i d = -4.2a v ds = -16v 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 1s 1ms 10ms 100ms dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) 0.01 0.05 0.1 0.2 duty=0.5 single pulse p dm duty factor = t/t peak t j = p dm x r thja + t a t t rq ja = 270c/w 0.75 x rated v ds to the oscilloscope -10 v d g s v ds v gs r g r d 0.8 x rated v ds to the oscilloscope d g s v ds v gs i d i g -1~-3ma 10 100 1000 10000 1 5 9 1 31 72 12 52 9 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz ciss coss crss
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 5 of 5 ssm230 5 gn 2/16/2005 re v.2.1


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